1. Field of the Invention
The present invention relates to testing memory arrays. More particularly, the present invention relates to a high speed method and circuit for testing non-volatile memory devices for address uniqueness.
2. Background Information
A conventional address uniqueness test in memory devices is a significant test in the memory device manufacturing process. Due to silicon defects in the address path, stuck-at-faults occur in the address path, which can cause address uniqueness to fail. The address uniqueness testing is done to screen bad components in a memory device having address uniqueness failure even before testing for the more time consuming memory program or erase write or read testing.
One such conventional technique of address uniqueness testing involves writing to and reading from the memory. In order to cover all the addresses, all address locations are written and read with unique data bytes. In another conventional technique, the method of uniqueness testing involves a single latch/flip-flop per word line and column line output that stores the state of the word line or column line. The word or column line is then serially sent to logic to identify if one and only one address is enabled. In yet another conventional case, the method involves the use of a ladder-like series configuration of transistors built over the rows and columns of the memory array.
FIG. 1 illustrates a circuit diagram 100 of a four word line ladder structure 115. The ladder structure 115 comprises a plurality of transistors (referenced as 101, 102, 103, 104, 105, 106, 107, 108, 109, 110 and 111) arranged in vertical and horizontal legs fed by an input coupled to a ground terminal (Vgnd). The output of the ladder structure 115 serves as inputs to a read out logic 112 (AND gate) via a parallel leaker resistance circuit that is charged by a power supply (Vpwr). The leaker resistance circuit comprises a first resistor leaker_0 113 and a second resistor leaker_1 114. The first leaker resistor 113 is further coupled to an input of the read out logic 112 via an inverter 116. The leaker resistance circuit is powered by a supply voltage (Vpwr). The gates of the transistors in the ladder structure 115 are controlled by word lines (W0, W1, W2, W3, W0b, W1b, W2b and W3b). The ladder structure 115 is triggered by a signal Vgnd from the top of the ladder structure through the horizontal and vertical legs to overcome a weak power supply signal (Vpwr) triggered through the second resistor leaker_1 114. The signal Vgnd further enables the read out logic 112 to identify one of the three ideal operating conditions of the word lines and to thereby provide an output (Pass/Fail) for the address uniqueness test. The three operating conditions for determining memory address uniqueness are: no word lines active; one word line active; and two or more word lines active.
The conventional methods for address uniqueness tests have limitations in terms of longer testing time and parallel operation of sensing and writing circuitries. Although the testing is done for address uniqueness alone, it may also show problems related to memory storage space and limitations of the ladder structure 115 with reference to speed for higher density memories.
It would be desirable to have an improved method and an analog circuit for address uniqueness test in memory devices, which will significantly decrease test time for high density non-volatile memories.